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Review: JTAGMaster Boundary Scan Tester

The JTAGMaster is a boundary scan interface controller for your PC with ports for all IC manufacturers including Altera and Xilinx. As well as for in-circuit programming of FPGAs, CPLDs and selected microcontrollers, you can use it for training purposes and to create test flows for production PC boards. It will provide you with a thorough introduction to boundary scan technology.

By Mauro Grassi

JTAG stands for “Joint Test Action Group”, a group of engineers from various companies like IBM, Texas Instruments and Philips that developed boundary scan technology.

It was originally called JETAG, where the E stood for European but that was dropped when it became misleading.

The group’s task was to develop a system for automated testing of PC boards given that it was becoming more costly and difficult using traditional test methods.

There is an estimated ten-fold increase in the cost of repair as you move from component level faults to module level to board level and so on. For many electronic manufacturers, this economic cost was unacceptable and it became important to develop a more feasible method of testing PC boards. The result was boundary scan technology.

Theory of Boundary Scan

Boundary scan technology was developed in the 1980s and 1990s as a way of overcoming major problems with traditional test methods that were compounded by advances in SMT (Surface Mount Technology) and PC board making (especially multi-layer boards).

Click for larger image
Fig.1: the basic structure of a single boundary scan cell. Each digital pin of a JTAG compliant device has an associated boundary scan cell (except power supply pins). This diagram shows the structure of the cell, which is logically equivalent but not necessarily illustrative of the implementation in silicon.

In fact, it only became an IEEE standard in 1991 and is now known as IEEE 1149.1: “Standard Test Access Port and Boundary-Scan Architecture”.

The traditional method of testing at the time involved a bed of nails fixture. This was literally a matrix of nails on which the device under test (DUT) was placed.

Connections to test points on the DUT were made via these nails that then allowed testing to be performed. The kind of defects which one could test for using a bed of nails fixture included shorts between adjacent tracks, open circuits, component orientation, dry solder joints and others.

As SMT progressed, device packages began to have many more pins than before and came in smaller and more physically constrained packages that made traditional testing near impossible.

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