Readers who built the GPS-Based Frequency Reference described in the March, April and May 2007 issues of SILICON CHIP may recall that in the third article we described some circuit changes to improve its short-term stability. These modifications were made in response to an email which had arrived from New Zealand reader Dr Bruce Griffiths, advising that the original method used for cascading the synchronous frequency dividers IC4, IC5 & IC6 was not the best way.
Fig.1: the revised divider circuit (all changes inside the highlighted area). IC4's TC output (pin 15) is now fed to IC5's CEP input (pin 7), while pin 10 now goes to +5V. IC5's TC output is fed via IC3e to the clock inputs of IC6a & IC6b, while the J & K inputs of these flipflops are now tied to the +5V rail.
When these changes were made, it did appear that the performance of the Frequency Reference had been improved. However, recent testing has shown that there is a better way to cascade the synchronous divider chain. It appears that the earlier changes created subtle problems in terms of divider instability – and as a result it was much easier than it should have been to set the Reference to “lock” onto a frequency other than the correct 10.000000MHz.
This became evident recently after quite a few hours were spent in testing the prototype of the GPS-Based Frequency Reference, with an equipment set-up which had the necessary measurement accuracy.
The main cause of divider instability turned out to be the way the “terminal count” output of the top decade divider IC4 (pin 15) was coupled to the “count enable carry” or CET input of IC5 (pin 10) in the next divider stage, instead of the “count enable” input of that chip (pin 7). From my reading of the 74HC160 device data back in 2007, it had seemed that this was the correct choice. However, recent testing showed that with this configuration there was a tendency for IC5 to be occasionally clocked on the ninth pulse from IC4, instead of the correct tenth pulse. As a result, there was a significant “jitter” in the nominal 100kHz output from IC5, as it effectively danced between frequencies varying between 100kHz and 111kHz.
After trying various circuit changes, a cure was found by swapping the connections to the CET and CEP inputs of IC5 – feeding the TC output of IC4 to the CEP input (pin 7) and connecting the CET input (pin 10) to +5V. IC4 and IC5 now divide down the crystal oscillator frequency by the correct factor of 100, with rock-steady reliability.
This revealed that there was another configuration error in the original circuit changes to convert the third divider stage (using IC6) to fully synchronous operation. The method chosen did work but had an unintended side effect: the output pulses of IC6a fed to the phase comparator IC7 were not the correct 50kHz pulses but were actually bursts of 5MHz pulses within the 50kHz pulse envelopes.
As a result, it was possible for the phase comparator to allow the overall frequency control loop to lock at a number of closely spaced different frequencies – only one of them being the correct 10.0MHz.